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Module PrepassSchedulingOracle

module PrepassSchedulingOracle: sig .. end

Prepass scheduler backend specific implementation

type iflift_mode =
| Default
| Ignore_Liveness
| Move_Stores 
type relsymbol = int 
type relvalue =
| RAdd of relsymbol * BinInt.Z.t
| RConst of BinInt.Z.t 
val relvalue_add : relvalue ->
       relvalue -> relvalue option
val relvalue_sub : relvalue ->
       relvalue -> relvalue option
val relvalue_add_imm : relvalue ->
       BinNums.coq_Z -> relvalue
val rel_abstract_analysis : bool
val rel_eval_op : Op.operation ->
       relvalue list ->
       relvalue option
val eval_reladdr : Op.addressing ->
       relvalue list ->
       relvalue option
val use_alias_analysis : unit -> bool
type rel_loc = {
   rel_loc_base : int;
   rel_loc_ofs : BinInt.Z.t;
   rel_loc_len : BinInt.Z.t;
} 
val overlap : BinNums.coq_Z -> BinNums.coq_Z -> BinNums.coq_Z -> BinNums.coq_Z -> bool
val can_interfere_rel : rel_loc -> rel_loc -> bool
val can_interfere_rel_opt : rel_loc option ->
       rel_loc option -> bool
val rel_loc_of_rv_chunk : relvalue option ->
       AST.memory_chunk -> rel_loc option
type abs_loc = {
   abs_loc_base : ValueDomain.aval;
   abs_loc_len : BinInt.Z.t;
} 
val abs_loc_of_av_chunk : ValueDomain.aval -> AST.memory_chunk -> abs_loc
val can_interfere_abs : abs_loc -> abs_loc -> bool
val can_interfere_abs_opt : abs_loc option ->
       abs_loc option -> bool
type loc = {
   abs_loc : abs_loc option;
   rel_loc_opt : rel_loc option;
} 
val default_loc : loc
val can_interfere : loc -> loc -> bool
val build_constraints : PrepassSchedulingOracleDeps.opweights ->
       (BTL.iblock * Registers.Regset.t) array ->
       'a ->
       iflift_mode ->
       bool -> InstructionScheduler.latency_constraint list
val get_inum : BTL.iblock * 'a -> int
val print_deps : InstructionScheduler.latency_constraint list ->
       (BTL.iblock * 'a) array -> unit
val resources_of_instruction : PrepassSchedulingOracleDeps.opweights -> BTL.iblock -> int array
val print_sequence : Stdlib.out_channel -> (BTL.iblock * Registers.Regset.t) array -> unit
val length_of_chunk : AST.memory_chunk -> int
val define_problem : PrepassSchedulingOracleDeps.opweights ->
       Registers.Regset.t ->
       RTLtyping.regenv ->
       bool ->
       ((Registers.reg, int * int) Stdlib.Hashtbl.t *
        (Registers.reg * bool) list array)
       option ->
       (BTL.iblock * Registers.Regset.t) array ->
       'a -> iflift_mode -> InstructionScheduler.problem
val add_sequentiality_constraints : int ->
       InstructionScheduler.latency_constraint list ->
       InstructionScheduler.latency_constraint list
val define_sequential_problem : PrepassSchedulingOracleDeps.opweights ->
       Registers.Regset.t ->
       RTLtyping.regenv ->
       bool ->
       ((Registers.reg, int * int) Stdlib.Hashtbl.t *
        (Registers.reg * bool) list array)
       option ->
       (BTL.iblock * Registers.Regset.t) array ->
       'a -> iflift_mode -> InstructionScheduler.problem
val zigzag_scheduler : InstructionScheduler.problem ->
       bool array -> InstructionScheduler.solution option
val prepass_scheduler_by_name : string ->
       InstructionScheduler.problem ->
       (BTL.iblock * 'a) array -> InstructionScheduler.solution option
val makespan_of_solution : 'a array -> 'a
val print_solution : int array -> unit
val solution_to_position : 'a array -> int array
val compute_greedy_makespan : PrepassSchedulingOracleDeps.opweights ->
       (BTL.iblock * Registers.Regset.t) array -> 'a -> int
val schedule_sequence : (BTL.iblock * Registers.Regset.t) array ->
       'a ->
       Registers.Regset.t ->
       RTLtyping.regenv ->
       bool ->
       (Registers.reg, int * int) Stdlib.Hashtbl.t *
       (Registers.reg * bool) list array ->
       iflift_mode -> (int array * int) option
val dubious_compute_greedy_makespan : (BTL.iblock * Registers.Regset.t) array -> 'a -> int