module KV3: sig .. end
val resource_bounds : int array
val nr_non_pipelined_units : int
val nlist_rec : 'a -> 'a list -> int -> 'a list
val nlist : 'a -> int -> 'a list
val bogus_register : Machregs.mreg
val bogus_inputs : int -> Machregs.mreg list
val insns_of_op : Op.operation -> int -> Asmvliw.basic list
val insn_of_op : Op.operation -> int -> Asmvliw.basic
val insns_of_cond : Op.condition -> int -> Asmvliw.basic list
val insn_of_cond : Op.condition -> int -> Asmvliw.basic
val insns_of_load : AST.trapping_mode ->
AST.memory_chunk -> Op.addressing -> int -> Asmblock.bcode
val insn_of_load : AST.trapping_mode ->
AST.memory_chunk -> Op.addressing -> int -> Asmvliw.basic
val insns_of_store : AST.memory_chunk -> Op.addressing -> int -> Asmblock.bcode
val insn_of_store : AST.memory_chunk -> Op.addressing -> int -> Asmvliw.basic
val latency_of_op : Op.operation -> int -> int
val resources_of_op : Op.operation -> int -> int array
val non_pipelined_resources_of_op : Op.operation -> int -> 'a array
val resources_of_cond : Op.condition -> int -> int array
val latency_of_load : 'a -> 'b -> Op.addressing -> int -> int
val latency_of_call : 'a -> 'b -> int
val resources_of_load : AST.trapping_mode -> AST.memory_chunk -> Op.addressing -> int -> int array
val resources_of_store : AST.memory_chunk -> Op.addressing -> int -> int array
val resources_of_call : 'a -> 'b -> int array
val resources_of_builtin : 'a -> int array